Just my 2cents on this. Folks, this is the base line that is being requested and being reached. It has taken decades and billions of $s if not a trillion + to reach the end of the line for CMOS technology. As stated, you have to start somewhere. 100nm is a very respectable size. I acknowledge the "every mm matters" crowd but realize that the 100nm is not the dimension of the chip. We have heard numbers from the company recently saying 20x speed and previously 50-100x. We also have been told that as the size shrinks by 1/3 the speed doubles. Given the massive speed increase even at a reported 20x current chips the architecture will be arranged to maximize usability of the chips given each and every different application. The relationship between foundry and designers is symbiotic and will work together for mutual benefit. No one wants a faulty product. You don't just take today's boards and plunk a POET chip on it. They will be complimentary and blistering fast. There may be other challenges with the limitations in the boards themselves but that is another post for later. Let's get the base line met and adoption of it into the mainstream and then start talking about reducing the size further. Anyone saying that "the next big thing needs to be as small as today's CMOS chip of 20 or 30 nm" does not understand the elasticity of product development and engineering. The boards will be built to accommodate the new chips as required.
Ok 5 cents. Derekwpg
