Hi! Author here.
It means that in the world of semiconductor logic, 100nm is too damn big for the modern microprocessor industry.
This is what I meant when I said that solutions are complicated. We've known about the characteristics of gallium arsenic (great band gap, high speeds, orders of magnitude above silicon for radiation hardening) for decades. In the 1980s, gallium arsenic was going to be the next-gen technology that *replaced* silicon in microprocessors. It didn't happen. Instead, gallium arsenide became a niche technology that's used in specialized areas where its particular benefits can be leveraged optimally.
The fact that POET has pushed down to 100nm is noteworthy considering that conventional GaAs has focused on much higher nodes. The benefits of being able to build in 100nm or below processes could have real utility for certain areas.
But consider Apple's A5X, at 103mm square in 28nm. Even though gate scaling is no longer linear, an A5X built on 100nm as opposed to 28nm would be 3-5x larger. That's 300-500mm or the size of a modern 15-core server processor.
You just can't effectively put that in a mobile phone. It would *wreck* the cost curve by driving wafer yields through the floor (At 300mm sq, you'd get 1/3 the dies per wafer). If we assume a $15-$20 price on the A5X now, you'd be looking at a $30-$45 price depending on defect density.
We have arrived at the current point because no one has yet managed to build a comprehensive alternative for silicon that provides all the necessary benefits *of* silicon and justifies investing in entirely different manufacturing technologies.
In this case, any replacement for modern silicon at 28nm must be able to allow a return to the cost-curve scaling of previous generation chips. Eliminating the need for double or quadruple patterning through a return to higher processes would not offset the cost of a 100nm-sized production.
