Yes that was great of Chris to let us know. It should be noted that with POETs unique design of integration if for example the customer was looking for a 100Gb/s transceiver this would require 2 VCSEL's and so on. How many can they fit on a chip I think would be more associated with a thermal limit rather than a space limitation? This is extremely exciting stuff because it does provide for a single chip optical integration of multiple VCSELs and if they are 50Gb/s the increase in capacity adds up really fast (no pun intended). Take this one step further and are they actually looking at an in plane VCSEL which would incorporate the ease of connection to the edge of the chip.
There are of course a number of advantages that enable this compact design.
-energy efficiency with dramatic reduction to the power budget and reduced generation of heat.
-cost reduction that will unparalleled in the industry
Go to time 19:54 to get an idea of the kind of designs that have been looking at.
http://www.vvcnetwork.ca/empireclub/20140428-taylor/
