POET Technologies Inc.

I get a ton of in-office mail, briefs, bulletins pertaining to our side of the industry and reading material from colleagues. Some of this you may have seen.

How Companies Approach Semiconductor IP Purchase Decisions

March 27, 2014

By Leslie Landers, Vice President of Worldwide Sales, Kilopass Technology Inc.

Design costs are accelerating as projects move to 65 nm and below which has given rise to the growing use of third party intellectual property blocks. According to IBS, typical chip design costs for a project in 2004 were about $18 million. Just over $1 million of this went towards the licensing and royalties associated with IP blocks used in the design. Today, typical per chip design costs approach $50 million. More than 25% of this is allocated to semiconductor IP costs.

In working with Kilopass non-volatile memory IP customers, we find the strategic benefits of incorporating semiconductor IP are clear but the selection process can be challenging.

Design teams are under pressure to complete complex chip designs in an environment characterized by shrinking market windows and intense unit price pressures. The loaded cost of a two person semiconductor design and verification engineering team can run over $400k a year. This drives companies to focus internal design efforts on elements that leverage the organization’s unique core competencies. Where practical, purchased semiconductor IP blocks help efficiently complete the design.

In converging on the specification and identifying the best semiconductor IP choice there are a number of important factors for semiconductor architects, designers and IP sourcing managers to consider.

Is the IP available in the foundry process node we are targeting?

For semiconductor IP that is acquired in a transistor-layout format (such as GDSII), both the specification and foundry process qualification are crucial. This makes it essential for a semiconductor IP provider like Kilopass to have a business model that is focused on close customer engagement and to continually provide a roadmap that addresses new nodes as they come online.

In the world of semiconductor IP, not every IP block is available for every foundry process node. At 28 nm, for example, individual foundries offer variants to address target performance, cost and power profiles. This can make it tricky for a design team and IP Manager to find what’s needed. Often, there will be one or more blocks that will require some non-recurring engineering work to obtain the needed fit.

What is the risk profile associated with incorporating the IP into our project?

Companies look to the process expertise of the IP provider along with the characterization and qualification data to anticipate quality and yield. There is less risk (and cost) in working with IP solutions that utilize standard CMOS and that avoid additional process steps.

It also helps if the IP provider has an established track record through high-volume shipments of the same (or very similar) IP blocks. Customers also can get a feel for IP quality by looking to the information, expertise and assistance available from the IP supplier.

Do the economics work?

The business model for most semiconductor IP involves varying combinations of technology license fees, non-recurring engineering costs, project support and volume based royalty payments. Business and IP managers map these costs to the design program to assess the return on investment.

Other factors can have a significant though less obvious impact on the economics. In some cases, an IP alternative that looks less expensive up front can cost more to implement. That’s certainly true if a candidate IP block entails non-standard foundry processing. In our business, customers with high volume applications also find programming time can significantly change the OTP memory cost profile.

As process geometries shrink, the rationale for purchasing semiconductor IP grows. At Kilopass we like to work with customers as they are thinking through the architecture for upcoming designs. This enables us to quickly determine if there’s a fit and to jointly tune specification details such as area, voltage requirements and programming needs for an implementation that maximizes project results. This interaction helps ensure we can deliver on the promise semiconductor IP can provide in a way that is robust, practical and cost effective.

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EileenTeahon
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