The article says they have scaled to 100nm. But it also says " Further scaling of our device portfolio is required. That should not prove too tricky, as based on our preliminary work on logic devices with 100 nm feature sizes,...." To me all of these phrases means they have scaled some of their devices down to that size in there own lab. That does not mean all of their devices have been shrunk, nor does it mean that the third party lab have validated the product either. If they are going to claim success in reaching a viable chipset at 100nm, they need a host of components all brought down to that size and working together as intended. There is no point shrinking just a Pfet and yelling from the tower, " We did it!!" What if the Nfet has a different approach needed to reach that size. All will come but the process is in discovery mode and they are feeling their way through this. This is no different than any of the other milestones to date. Until the technology is replicated successfully using their recipe, it is not validated. Perhaps that is why they are not considering the article having material information ( therefore no NR). It will come once the fab demonstrates that they can replicate the process to have a working device with the performance obtained in UConns labs. Therefore, ms8 is complete when we hear it is done with third party validation, not before. Not far now. Derekwpg
