This is interesting good find, I'd just like to say that looking at the plot they provided....that transistor works, but has poor performance. It doesn't turn 'off' or 'on' as hard as higher node standard CMOS....also it is 'depletion' type, which is not suitable for complementary logic 'CMOS'.

This does seem to be the fate of CMOS. Just want to say that the hole mobility is for the P-channel transistor, usually the slower carrier.

The lower power consumption of a poet circuit, is do to a REDUCED operating voltage, afforded by the mobility advantage of GaAs. Maybe a typo in fairchij's earlier post about that increased voltage operation?

Absolutely, in the mean time though, chip-to-chip optical interfaces will be a big market in data centers I believe.

Also to be clear, the white paper is about optical interconnects...used to connect processors, optically. Not about processor technology, such as the IBM link somebody posted earlier today.

Hope this helps clarify.

In the white paper, POET is saying it's proposed optical interconnect is different than IBMs, and should perform better and be cheaper.