Patriot Scientific

The Markman is basically the decision of what the important terms in the trial will mean... The Defendants want theirs.. the Plaintiffs want theirs... after hearing their arguments, the Judge decides what the definition of those terms will be...

The Markman Ruling by Judge Ward June 15th 2007... East Texas

Wolf has broken this Markman ruling down. This will help the laymen understand the ruling.

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TPL/PTSC--Green

Defendant----Red

Court--------Blue

The parties have agreed to the construction of the following terms.

1. ‘336 Patent

“Oscillator” means “a circuit capable of maintaining an alternating output.” “On-chip input/output interface” means “a circuit having logic for input/output communications, where that circuit is located on the same semiconductor substrate as the CPU (claims 1-2, 6-10) or the microprocessor (claims 3-5).” “Integrated circuit” means “a miniature circuit on a single semiconductor substrate.” “External memory bus” means “a group of conductors coupled between the I/O interface and an external storage device.”

2. ‘148 Patent

“Integrated circuit substrate” means “a single supporting material upon or within which is formed a miniature circuit.”

3. ‘584 Patent

“Instruction” means “a command to a processor that tells the processor what operation to perform.” “Boundary of said instruction groups” means “beginning or end of an instruction group.” “Supplying, from said instruction groups, using the predetermined location, said operand or instruction or both to said central processing unit” means “using the results of the locating step in the step of transferring the bits from the accessed operand or instruction to the central processing unit.” “Instruction register” means “a hardware element that receives and holds an instruction group as it is extracted from memory; the register either contains or is connected to circuits that interpret the instructions in the group.”

B. Disputed Constructions

1. 336 Patent

A. Central Processing Unit

The plaintiffs propose an electronic circuit that controls the interpretation and execution of programmed instructions.

The defendants propose the central electronic circuit in a computer that controls the interpretation and execution of programmed instructions.

The Court construes the term to mean an electronic circuit on an integrated circuit that controls the interpretation and execution of programmed instructions.”

B. Microprocessor

The plaintiffs propose an electronic circuit that executes programmed instructions and is capable of interfacing with input/output circuitry and/or memory circuitry.

The defendants propose an electronic circuit that uses a central processing unit to interpret and execute programmed instructions.

The court construes microprocessor to mean an electronic circuit that interprets and executes programmed instructions.

C. Ring Oscillator

The plaintiffs contend that this term means an oscillator having a multiple, odd number of inversions arranged in a loop.

The defendants propose an [oscillator] having an odd number of inverting logic stages connected in a loop.

The plaintiffs have the better argument. The extrinsic evidence cited by the defendants also supports the plaintiffs’ construction. It states that timers are built as chains of inverters, not just one inverter. Defendants’ Claim Construction Brief, Ex. U, MEAD & CONWAY, INTRODUCTION TO VLSI SYSTEMS (1980), at 234. Accordingly, the Court adopts the plaintiffs’ proposed construction.

D. An entire ring oscillator variable speed system clock in said integrated circuit

The plaintiffs argue that this term means a ring oscillator that generates the signal(s) used for timing the operation of the CPU, capable of operating at speeds that can change, where the ring oscillator is located entirely on the same semiconductor substrate as the CPU.”

The defendants’ proposed construction is “a [ring oscillator variable speed system clock] that is completely on-chip and does not rely on a control signal or an external crystal/clock generator.

The Court agrees with the defendants that the applicant disclaimed the use of an input control signal and an external crystal/clock generator to generate a clock signal. See Response to Office Action, April 11, 1996, at 8; Response to Office Action, January 13, 1997, at 4; Response to Office Action, July 7, 1997, at 3-4. Accordingly, the Court construes the term to mean “a ring oscillator variable speed system clock that is located entirely on the same semiconductor substrate as the CPU and does not directly rely on a command input control signal or an external crystal/clock generator to generate a clock signal.

E. Variable Speed

The plaintiffs’ proposed construction is “capable of operating at speeds that can change.”

The defendants argue that the term means “a speed (frequency) that is not tightly controlled and varies more than minimally.”

The Court construes the term to mean “capable of operating at different speeds.”

F. System Clock and Variable Speed Clock

The plaintiffs propose a circuit that generates the signal(s) used for timing the operation of the CPU.

The defendants contend that the term means “a circuit that is itself responsible for determining the frequency of the signal(s) used for timing the operation of the CPU.

Accordingly, the Court adopts the plaintiffs’ proposed construction.

G. “Oscillator Clocking”

The plaintiffs contend that no construction is necessary, but if a construction is required, they propose “the oscillator generates the signal(s) used for timing the operation of the CPU.

The defendants propose an oscillator that is itself determining the frequency of the signal(s) used for timing.

The Court agrees that the term requires construction. The Court construes the term to mean “an oscillator that generates the signal(s) used for timing the operation of the CPU.”

H. Processing Frequency

The plaintiffs propose “the speed at which the CPU operates.

The defendants propose “fastest safe operating speed.”

In the Court’s view, the applicants did not clearly define or limit the term “processing frequency.” Accordingly, the Court adopts the plaintiffs’ proposed construction.

<?xml:namespace prefix = st1 ns = "urn:schemas-microsoft-com:offi... />I. Processing Frequency Capability

The plaintiffs propose the range of speeds at which the CPU can operate.

The defendants propose “fastest safe operating speed at which the CPU can operate.

The Court construes the term to mean the speeds at which the CPU can operate.

J. Varying Together 2

The plaintiffs contend that the term means “both increase or both decrease.

The defendants’ proposed construction is “increasing and decreasing by the same amount

The Court construes the term to mean increasing and decreasing proportionally.

K. Second Clock

The plaintiffs’ proposed construction is a clock not derived from the first clock.

The defendants contend that no construction is necessary, but if construction is necessary, then they propose another clock.

The defendants appear to agree that the first clock is independent of the second clock. In any event, the independence of the second clock is required by the claim language. Accordingly, the Court declines to construe this term.

l. External Clock

The plaintiffs propose a clock not derived from the first clock, and which is not originated on the same semiconductor substrate upon which the entire variable speed clock is located.

The defendants contend that no construction is necessary, but if a construction is necessary, then they propose a clock not on the integrated circuit substrate.

The defendants have the better argument. One of ordinary skill in the art would understand the term independence to mean “two-way independence. Accordingly, the Court construes the term to mean “a second clock wherein a change in the frequency of either the second clock or ring oscillator system clock does not affect the frequency of the other.

N. External clock is operative at a frequency independent of a clock frequency of said oscillator”

The plaintiffs propose a change in the frequency of the oscillator (claims 6-9) or the variable speed clock (claim 10) does not affect the frequency of the external clock.

The defendants propose an external clock wherein a change in the frequency of one of the external clock or oscillator does not affect the frequency of the other (claim 6).

The Court construes the term to mean an external clock wherein a change in the frequency of either the external clock or oscillator does not affect the frequency of the other.

O. Fixed Frequency

The plaintiffs contend that no construction is necessary, but if the court determines that a construction is needed, then they propose a non-variable frequency.

The defendants propose having a speed that is tightly controlled and varies minimally.

This term is not a technical term and can be understood according to its plain and ordinary meaning. Accordingly, the Court declines to construe this term.

2. 148 Patent

A. Processing Unit

The plaintiffs propose an electronic circuit that controls the interpretation and execution of programmed instructions.

The defendants do not appear to dispute the plaintiffs’ proposal.

Accordingly, the Court adopts the plaintiffs’ proposed construction.

b. Memory and A Memory

The plaintiffs propose all of the storage elements on the substrate and the control circuitry configured to access the storage elements.

The defendants claim that this term is indefinite, but if construction is possible, they propose an information storing array that does not include registers

Accordingly, the Court construes memory to mean storage elements other than column latches.

C. Total area of said single substrate or total area of said substrate

The plaintiffs propose the total surface of the supporting material upon or within which is formed an interconnected array of circuit elements.

The defendants propose area enclosed by the outermost edges of the substrate.

The Court construes the term to mean the total top surface area of the

substrate.

D. Area of said single substrate or area of said substrate

The Court construes this term to mean the top surface area of the substrate.

E. Variable

This is not a technical term that requires construction and may be understood according to its plain and ordinary meaning. The Court declines to construe this term.

F. System Clock

The Court adopts its previous construction of this term in the 336 patent. See Section IV(B)(1)(f).

G. Ring Oscillator

The Court adopts its previous construction of this term in the ‘336 patent. See Section IV(B)(1)(c).

H. A ring oscillator having a variable output frequency

The Court adopts its previous construction of ring oscillator in the ‘336 patent. See Section IV(B)(1)(c). No further construction of this term is necessary.

I. The [ring oscillator] disposed on said integrated circuit substrate

The Court adopts its previous construction of “ring oscillator” in the ‘336 patent. See Section IV(B)(1)(c). No further construction of this term is necessary.

J. Interface ports for interprocessor communication

The plaintiffs contend that no construction is necessary. Alternatively, if a construction is needed, then the plaintiffs propose channels through which data can be transferred between two separate processing units.

The defendants propose channels through which data is transferred between two separate processing units.

The Court construes the term to mean channels through which data is allowed to be transferred between two separate processing units.

3. 584 Patent

A. Microprocessor

The Court adopts its previous construction of this term in the ‘336 patent. See Section IV(B)(1)(b).

B. Central Processing Unit

The Court adopts its previous construction of this term in the ‘336 patent. See Section IV(B)(1)(a).

C. Instruction Groups

The plaintiffs’ proposed construction is sets of from 1 to a maximum number of sequential instructions, each set being provided to the instruction register as a unit and having a boundary.

The defendants propose sets of from 1 to a maximum number of sequential instructions, in which the execution of the instruction depends on each set being provided to the instruction register as a unit and in which any operand that is present must be right justified and which cannot encompass a single 32-bit traditional conventional instruction.

The Court construes instruction groups to mean sets of from 1 to a maximum number of sequential instructions, each set being provided to the instruction register as a unit and having a boundary, and in which any operand that is present must be right justified.”

D. Operand

The plaintiffs argue that the term means an input to an operation specified by an instruction that is encoded as part of the instruction.

The defendants propose an input to a single operation specified by an instruction that is encoded as part of the instruction where the size of the input can vary depending on the value of the input.

The Court construes the term to mean an input to a single operation specified by an instruction that is encoded as part of the instruction where the size of the input can vary.

E. Said instruction groups include at least one instruction that, when executed, causes an access to an operand or instruction or both

The plaintiffs propose “the instruction being executed causes the CPU to use an immediate operand or execute a second instruction which is not the next sequential instruction.

The defendants’ proposed construction is the instruction being executed causes the CPU to use data or execute a second instruction.

The intrinsic evidence does not support the limitation proposed by the plaintiffs. Accordingly, the Court construes the term to mean the instruction being executed causes the CPU to use an operand or execute a second instruction.

F. Said operand or instruction being located at a predetermined position from a boundary of said instruction groups

The plaintiffs propose the immediate operand or the instruction that is accessed has a position, relative to the beginning or end of the instruction group that includes the operand or instruction being accessed, that is determined based on a portion of an accessing instruction that identifies an operation to be performed and without reference to operand or address bits in the accessing instruction.

The defendants propose the bits forming the accessed operand or instruction either begin or end at a position defined in relation to the boundaries of the instruction group in the instruction register rather than the currently executing instruction.

The Court construes the term to mean the operand or instruction is accessed at a position defined in relation to the boundaries of the instruction group that includes the operand or instruction being accessed.

G. Decoding said at least one instruction to determine said predetermined position

The plaintiffs contend that the term means interpreting an instruction, in particular the

portion thereof that signifies the operation to be performed, in order to identify a position relative to the beginning or end of the instruction group that includes the operand or instruction being accessed, without reference to the operand or address bits in the instruction being interpreted.

The defendants propose interpreting an instruction, in particular the portion thereof that signifies the operation to be performed, in order to identify a position relative to the beginning or end of the current instruction group.

The Court construes the term to mean interpreting an instruction, in particular the portion there for that signifies the operation to be performed, in order to identify a position relative to the beginning or end of the instruction group that includes the operand or instruction being accessed.”

H. Locating said predetermined position

The plaintiffs argue that this term means establishing operand or instruction supply within the instruction group that includes the operand or instruction being accessed at the predetermined position.

The defendants argue that the term means using the results of the decoding step to ascertain the address of the accessed operand or instruction by referencing the current instruction group address rather than the current executing instruction address without adding or subtracting an operand with the current Program Counter.

The Court construes the term to mean locating the operand or instruction within the instruction group that includes the operand or instruction being accessed at the predetermined position.

V. Conclusion

The Court adopts the constructions set forth in this opinion for the disputed terms of the ‘336 patent, the ‘148 patent, and the ‘584 patent. The parties are ordered that they may not refer, directly or indirectly, to each other’s claim construction positions in the presence of the jury. Likewise, the parties are ordered to refrain from mentioning any portion of this opinion, other than the actual definitions adopted by the Court, in the presence of the jury. Any reference to claim construction proceedings is limited to informing the jury of the definitions adopted by the Court.

Signed By Judge Ward