As a follow-up to the post where I didn't see the term "ring oscillator" in the Talbot patent:

On page 13 of the Request for Ex Parte Reexamination of the 148 patent is where the "ring oscillator" term is introduced. In the footnote it is admitted that Talbot does NOT use the term "ring oscillator", but it is stated that it is clear that figure 3 (of the Talbot patent) is a "ring oscillator." On page 14 the three (odd number) inverting elements are indicated by dashed arrows. One inverter is a Schmitt Trigger, one is a standard inverter, and one CMOS inverter is comprised of 2 transistors.

These 3 inverting elements, along with capacitors to regulate the delays, is not, based upon my understanding, a "standard ring oscillator." Such a standard ring oscillator would be a chain of standard inverters (odd number), and the gate delay associated with each inverter would be summed to generate a total delay between inverted pulses (clock pulses).

Of course, this "ring oscillator" term is a debatable issue. A current EE opinion would be welcome.

However, even if this Voltage Controlled Oscillator (VCO) of Talbot is a "ring oscillator" it is a subset of a timing device that is clocked externally.

From the Talbot patent:

"It will be seen from the description given above that the timing apparatus described including the phase locked loop is able to provide high frequency timing signals upon the application of a low frequency clock to the input thereof.

It thus becomes possible to supply a microcomputer incorporating apparatus on the same chip the timing as shown in FIG. 1. The user than needs only to connect the clock input pin 3' to a standard low frequency clock signal, at say 5 MHZ, to obtain operation of the microcomputer at high operating speeds."

The 148 and 336 ring oscillator runs independently of any external clock and varies together with the processor it is clocking. As I said before, this is the main selling point of the invention. I'm confident that TPL will point this out in their rebuttal.

Ledzius 4,691,124

My Summary Interpretation:

Ledzius describes a Special Purpose Algorithm circuitry clocked by on-same-chip clock generator circuitry. Clock circuitry is designed so clock frequency “matches” the critical path (slowest path) propagation delay of the entire Special Purpose Algorithm circuitry.

Clock generator does not use “ring oscillator.” Most delays implemented with series of OR gates.

Special Purpose Algorithm circuitry is NOT a microprocessor (it does not interpret and execute programmed instructions). It only crunches data input to produce resulting output.

There is No second CPU on the IC to control memory access

There is No second clock on the IC (which independently clocks the second CPU)

The only I/O interface on the IC are latches (no second CPU).

336

My Summary Interpretation:

336 describes a dual-CPU invention on one IC. The primary CPU is clocked by varying speed ring oscillator, while the I/O CPU is clocked by another (independent) clock on the IC. The “ASYNCHRONOUS/SYNCHRONOUS CPU” paragraph (below) summarizes the benefits of the invention as it pertains to running both the primary and the I/O CPU’s optimally.

From Patent:

“Details of the microprocessor 50 are shown in FIG. 2. The microprocessor 50 includes a main central processing unit (CPU) 70 and a separate direct memory access (DMA) CPU 72 in a single integrated circuit making up the microprocessor 50.”

“The DMA CPU 72 controls itself and has the ability to fetch and execute instructions. It operates as a co-processor to the main CPU 70 (FIG. 2) for time specific processing.”

Ledzius uses similar language to that below to describe advantages of having clock on same IC as “primary” circuitry. 336 is for a microprocessor, while Ledzius is for special purpose processing circuitry. 336 uses ring oscillator, while Ledzius does not.

From 336 Patent:

OPTIMAL CPU CLOCK SCHEME

The designer of a high speed microprocessor must produce a product which operate over wide temperature ranges, wide voltage swings, and wide variations in semiconductor processing. Temperature, voltage, and process all affect transistor propagation delays. Traditional CPU designs are done so that with the worse case of the three parameters, the circuit will function at the rated clock speed. The result are designs that must be clocked a factor of two slower than their maximum theoretical performance, so they will operate properly in worse case conditions.

The microprocessor 50 uses the technique shown in FIGS. 17-19 to generate the system clock and its required phases. Clock circuit 430 is the familiar "ring oscillator" used to test process performance. The clock is fabricated on the same silicon chip as the rest of the microprocessor 50.

The ring oscillator frequency is determined by the parameters of temperature, voltage, and process. At room temperature, the frequency will be in the neighborhood of 100 MHZ. At 70 degrees Centigrade, the speed will be 50 MHZ. The ring oscillator 430 is useful as a system clock, with its stages 431 producing phase 0-phase 3 outputs 433 shown in FIG. 19, because its performance tracks the parameters which similarly affect all other transistors on the same silicon die. By deriving system timing from the ring oscillator 430, CPU 70 will always execute at the maximum frequency possible, but never too fast. For example, if the processing of a particular die is not good resulting in slow transistors, the latches and gates on the microprocessor 50 will operate slower than normal. Since the microprocessor 50 ring oscillator clock 430 is made from the same transistors on the same die as the latches and gates, it too will operate slower (oscillating at a lower frequency), providing compensation which allows the rest of the chip's logic to operate properly.

From 336 Patent:

ASYNCHRONOUS/SYNCHRONOUS CPU

Most microprocessors derive all system timing from a single clock. The disadvantage is that different parts of the system can slow all operations. The microprocessor 50 provides a dual-clock scheme as shown in FIG. 17, with the CPU 70 operating a synchronously to I/O interface 432 forming part of memory controller 118 (FIG. 2) and the I/O interface 432 operating synchronously with the external world of memory and I/O devices. The CPU 70 executes at the fastest speed possible using the adaptive ring counter clock 430. Speed may vary by a factor of four depending upon temperature, voltage, and process. The external world must be synchronized to the microprocessor 50 for operations such as video display updating and disc drive reading and writing. This synchronization is performed by the I/O interface 432, speed of which is controlled by a conventional crystal clock 434. The interface 432 processes requests for memory accesses from the microprocessor 50 and acknowledges the presence of I/O data. The microprocessor 50 fetches up to four instructions in a single memory cycle and can perform much useful work before requiring another memory access. By decoupling the variable speed of the CPU 70 from the fixed speed of the I/O interface 432, optimum performance can be achieved by each. Recoupling between the CPU 70 and the interface 432 is accomplished with handshake signals on lines 436, with data/addresses passing on bus 90, 136.

Above Green is very important difference in my opinion. However, I don't know what is the important point(s) TPL is using to determine infringing products.