I to have been wondering what they are building at BAE?
On looking back further to the JAN 8 news release (section below). We know the 3rd party foundry is BAE and I'm guessing that the fact they are transisitioning from lab to fab and that in the lab "efforts have been geared towards HFET transistors" we can assume this is what they are working on.
I'm not sure what HFET transistors are used for specifically - But I do believe that this element of BAE work is focused at a different market verticle to Andigics and the VSCEL. I further agree that this development work is more advanced than the VSCEL.
Kind regards
"Lab-to-Fab" Transition: 100-nm and 40-nm Scaling Program Update
POET recently reported a contractual effort with a "3rd party foundry" to accelerate the transition from "Lab-to-Fab" of the POET technology to a manufacturing status at the 6" wafer scale. Significant progress has been made towards transfer of critical manufacturing steps to the "3rd party foundry". This flow will both accelerate and improve quality of results for prototype fabrication and test supporting process flow and design enablement kit development. Efforts in the lab have been geared towards optimization of the self-aligned contacts for the HFET transistors, as well as on optimization of the vertical structure of the devices. Mr. Daniel DeSimone, Chief Technology Officer noted: "We have seen positive improvement in the key figures of merit we test for in our devices. We see further possible improvements and are continuing to work on device and process flow to achieve the highest possible performance."
In a parallel development at the UCONN lab, a new additional sputter tool was received and accepted. The tool is nearing completion of internal qualification. Deployment of the new tool will drastically reduce prototype fabrication cycle times as well as improve the quality and process control of key films used in the process flow. These will be critical not only to current development, but also necessary for transfer to eventual manufacturing stages.
Milestone Updates
PET Foundation Process Design Kit ("PDK") targeting 40-nm - Sentaurus modeling (a Synopsys tool) has been performed with new fabrication innovations to achieve controlled scaled device operation. These modeling predictions are guiding and confirming the device prototype development and testing. The PDK milestone has been moved to Q1 2015 so that the release incorporates the latest innovations currently being developed in the UCONN Lab and in parallel with the "3rd party foundry".
"3rd Party Foundry" 40/100-nm Transfer - This "Lab-to-Fab" effort requires bringing up critical layers manufacturing capability in our "3rd party foundry" which enables more complex test structures. Significant progress has been achieved towards the completion of this milestone. The Company is very close to completing qualification runs for the flow in which the critical layers are performed at our "3rd party foundry". This new flow will significantly accelerate completion and optimization of development on 100 and 40-nm foundation devices and associated proof of concept optical and electronic circuit structures.
