The reference to TSMC is very interesting.
Recall POETs announcement on Sept 2
POET ANNOUNCES A COLLABORATION WITH THIRD PARTY FOUNDRY TO REPRODUCE AND ENHANCE REPEATABILITY OF THE 100-NM RESULTS AND SHRINK ITS PLANAR ELECTRICAL TECHNOLOGY PROCESS (PET) TO 40-NM SCALE
That same day they announced this in a separate announcement:
POET TECHNOLOGIES AND SYNOPSYS COLLABORATE ON ADVANCED MODELING OF PLANAR ELECTRICAL TECHNOLOGY AND DEVELOPMENT OF POET'S FIRST PROCESS DESIGN KIT
Then 6 months later they announced the agreement with BAE and in the same NR they announce the appointment of Tony Blevins to the POET Technology Roadmap Advisory Committee.
It is possible that the Sept 2 Third Party Foundry facility was with TSMC? I think that many of us at the time assumed it was Global Foundries.
Interestingly reference was made to this article as the reason 40 nm was selected as the target node to compete with 16 nm FinFET without the costs being spent by TSMC.
http://www.eetimes.com/document.asp?doc_id=1324299&.
To recap the reference made today by Shandlar
Sept 2014 article from when they had a working 100nm process and needed capital to commercialize. They obtained said capital, and are selling components currently on this process. They apparently also have prototypes of new components on the 40nm process now using a retired and retrofitted TMSC foundry to be on sale this year.
It is all very intriguing but I expect that if it was true (which we have no evidence to support) then POET would not want that can of worms opened up.
