What chipmakers will need to address growing complexity, cost of IC design and yield ramps
By Bruno Mourey, Chief Technology Officer, CEA-Leti
As these early days of the Internet of Things show the network’s promise and reveal technological challenges that could threaten its ability to meet user expectations in the years ahead, technology providers will be charged with supplying the solutions that will meet those challenges
Chief among them for designers and chipmakers are the increased complexity and cost of IC design and yield ramp-ups, and wafer costs, said Carlo Reita, strategic marketing manager at CEA-Leti.
“Disruptive architecture and integration technologies are required,” Reita told participants at the 17th annual LetiDays in Grenoble, France, June 24-25. In his talk, “Technologies and architectures for low-power data processing,” Reita noted the spikes in both complexity and cost that accompany the industry’s progression to smaller technology nodes. The spikes are driven primarily by costly new tools and increases in both design manpower and the number of expensive licenses for software-design tools that accompany increasing device complexity.
Adding yield ramp-up costs to IC design costs, which include both new designs and specializations, the projected NREs skyrocket from $59 million at 28nm to $176 million at 16nm and $2.24 billion at 5nm. Meanwhile, the average selling price of 300mm wafers grow from $9,885 at 16nm to $19,620 at 5nm.
Reita noted that such projections underscore the pressure that the industry will face to develop new design-implementation approaches that change the cost metrics for advanced-features, so that initial products can generate revenues that justify the design and yield ramp-up costs.
He said that managing data traffic that is increasing exponentially, while maintaining data-center server performance and lowering the centers’ energy consumption, is among the top challenges for the computing industry in the years ahead. Meanwhile, mobile computing and the Internet of Things are adding a different set of challenges that will feed the design-cost escalation, ranging from the requirement for mandatory long battery life to supporting heterogeneous and power-hungry applications and the capability to adjust to process, voltage and temperature variations.
........full article here... http://electroiq.com/blog/2015/06/what-chipmakers-will-need-to-address-growing-complexity-cost-of-ic-design-and-yield-ramps/
