I posted the full article in the off topic forum.
Toshiba Standardizes on IC Compiler II for Physical Design PR Newswire Synopsys, Inc. March 9, 2015 /PRNewswire/ -- Highlights: IC Compiler II enables Toshiba's successful tapeout of advanced 40-nm SoC 6X faster design turnaround time with one-third of the memory footprint 60 percentf smaller buffer area during clock tree synthesis delivers superior design area and power QoR Seamless handling of multiple modes and corners reduces timing ECO iterations Synopsys, Inc. (SNPS) today announced that its IC Compiler™ II place and route solution has enabled Toshiba to accelerate tapeout of an advanced 40-nanometer (nm) system on chip (SoC).
------- Wonder If any of this development at 40nm was done with POET in mind?
