Zvi Or-Bach, Founder, MonolithIC 3D Inc
Intel is right: heterogeneous integration enabled by 3D IC "increasingly important part of scaling."
At the recent ISSCC Intel presented the following slide. Quoting from Extremetech coverage: "At 10nm and below, the path forward will become increasingly murky. What Intel has proposed is essentially a shift towards other types of cost-saving technologies and process adoptions rather than relying on strict lithography improvement. Intel may be keeping its next-generation materials and lithography plans quiet, but the company does intend to push the envelope in other ways. 2.5D and 3D integration will be critical to the development of next-generation SoCs."....
........A recent validation of the unreasonable costs associated with dimensional scaling beyond 28 nm could be calculated from a recent EE Times articleTSMC to Start 10nm in 2017, Closing Gap with Intel. Quoting: "By the end of 2018, the company’s Taichung site will reach a monthly output capacity of 90,000 wafers at the 10nm and more advanced technology nodes, according to a report on the Chinatimes.com website. TSMC earlier this month said it would invest NT$500 billion ($15.9 billion) as part of an expansion at the Taichung site in central Taiwan." At two year’s depreciation, this represents $7,400 per wafer!!!
http://www.eetimes.com/author.asp?section_id=36&doc_id=1325921&_mc=sm_eet
