The high growth segments of the electronics industry are mobile devices powered by tiny, light weight batteries. An important figure of merit for these devices is the number of hours they can operate on a single battery charge. Designs groups are incentivized on their ability to remove a few milliwatts from the operation of a mobile device.
The power required by a smartphone application processor is continually being squeezed and the success of a product might depend on the hours between battery charges.
While all this work is being done on the application processor, that pesky DRAM is being continually refreshed…and using power. That DRAM is being refreshed even when your smartphone is in your pocket. When you push the start button everything comes to life right where it was when you let it go to sleep. If the phone had been completely powered down it would have had to re-boot DRAM for a minute before you could make a call or write a text message. That would be quite annoying.
So the DRAM is drawing power all the time because it is a volatile memory. Why don't we use the non-volatile NAND for main memory and save all that DRAM power? NAND, in the world of microprocessors, is tortuously slow and it is not random access, and NAND memory would actually wear out in a second or two if it were used as RAM.
A memory technology that has all the characteristics of DRAM but would hold data when power is off would make a super low standby power smartphone possible. We would call such a memory technology "non-volatile system RAM". Such a technology would be the first non-volatile RAM since the ancient core memory discussed above.
http://seekingalpha.com/article/2664155-intel-memory-the-solution-to-the-mobile-problem?uprof=46&dr=1
This of course is one of solutions POET offers…
A static RAM memory cell in CMOS requires 8 resistors. POET can do this with one thyristor and one load device (2 device memory cell). But the big kicker to keep in mind as you read this article is that POETs thyristor is capable of providing all memory replacement solutions. The thyristor can function as non-volatile memory cell. It can also function as a static memory cell that does not require to be continually refreshed adding to battery drain. Big for mobile devices but very applicable to the energy and backup requirements at the data center CAPEX and operating costs.
Here is what is in the POET CP
- POET supports a high speed, very high density thyristor-based universal memory
cell
- A single memory array can be operated as an SRAM, a DRAM, or NVRAM
depending on controller configuration
- NVRAM capability is phase-change type so no write-based device reliability issues
like NAND flash
- Can eliminate need for dedicated NVRAM for system backup and recovery since all
embedded memories already have NVRAM capability
- Density comparable to leading edge DRAM, and much higher than existing SRAM,
NAND flash, NOR flash, or PCRAM technologies
- Wide band gap material provides much higher noise immunity than Silicon-based
technologies (several orders of magnitude improvement in soft error rates)
This is the patent covering POET memory:
https://www.google.com/patents/US20140241660?dq=geoff+taylor&hl=en&sa=X&ei=PfcJVP_6INa3yASrxoLYDQ&ved=0CCYQ6AEwAQ
