Think optical clock and 10GHz. Something the silicon industry will never be able to achieve with III-V channel implants even if they can solve for the lattice mismatch and dislocation. III-V is much more tolerant to heat but it also has much lower thermal transfer capability and very different thermal expansion coefficients so hot spots are going to be much more problematic especially with the reduced transfer area caused by the FIN. The silicon industry is having extreme difficulty and delays just using the materials they know to implement FinFET at 14nm and 10nm. Without EUV going forward their process will require much greater accuracy dealing with increasing mask numbers all at much higher costs. Recall SG discussing the $500k cost for the 40nm mask set for POET versus $10 million for FinFET.
These companies (the Intel’s) will be forced to deal with POET at a time when POET has already achieved significant partnerships. It is going to be fun to watch the light go on.
Again apart from everything else think 10GHz enabled by an optical clock at a significant power reduction. It is something that silicon will never do so not only does POET offer this cheaper solution and massive integration to reduce the chip count and assembly costs it also exceeds any performance levels that can be achieved with silicon with very large energy savings. Would you like an ultra-thin smart phone/tablet/watch with that POET chip or a regular size that gets charged once or twice a week. Or would you prefer the no charge model that incorporates the POET solar cell.
Remember where the true strength of POET resides. It is that capability to integrate multiple functions on one chip that today require multiple chips. And it offers the best capabilities of analog, digital and optical on thast single chip without sacrifice. Which is again something that silicon will never do.
