POET Technologies Inc.

Q1-15: currently 1st in the list is PET Foundation PDK (Process Design Kit) targeting 40nm (V 1.0)
Definition: Design rules and parameters library models for PET process. Devices include complimentary HFET and HBT transistor and a thyristor with both optical and electrical operation.

Q1-15: 3rd and 4th on the list is Electrical 100nm Ring Oscillator & 50GHz VSCEL
- physical measurement tools for the electrical and optical capabilities of the chips
- where software functionality simulation ends.

From http://www.cmc.ca/en/WhatWeOffer/Design/Kits.aspx
Design kits typically consist of technology files and device libraries. Combined with the CAD tool, kits allow you to design an integrated circuit in a specific process technology. Analog and digital circuit design and layout are usually supported.

• Mask layer information to enable creation of integrated circuit layouts
• DRC (design rule check) rules to check the layout for conformance with manufacturing rules
• Schematic components, circuit simulation models and layout extraction rules to enable simulation of both schematics and layouts
• LVS (layout versus schematic) rules to assist with design verification (do my schematic and layout represent the same circuit?)
• Characterized device libraries with digital logic cells, analog cells, input/output pads, and more Datasheets on the cells
• Numerous technology files that configure the CAD tools correctly for startup, configuration, maintenance, and bug fixes
• Additional technology files, filter scripts and documentation on exporting a design from Synopsys tools and importing into Cadence tools
• Documentation to assist the user with the design flow. Designs can be captured with the layout editor, schematic editor, HDL (Verilog and VHDL) editors or imported via GDSII, EDIF, Verilog, or VHDL. Output is usually an integrated circuit design in GDSII format, ready for fabrication.

http://en.wikipedia.org/wiki/Process_design_kit
A process design kit (PDK) is a set of files used within the semiconductor industry to model transistors for a certain technology for a certain foundry, different kinds of libraries to be used with design software tools like NI AWR (for RFIC/MMIC/LTCC).

Typical PDK contains:

• standard cells library
• design rules (DRC rules)
• simulation model of transistors (typically SPICE)
• layout information (most commonly in GDSII format

Design Rule Checking or Check(s) (DRC) is the area of Electronic Design Automation that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called Design Rules. Design rule checking is a major step during Physical verification signoff on the design, which also involves LVS (Layout versus schematic) Check, XOR Checks, ERC (Electrical Rule Check) and Antenna Checks. For advanced processes some fabs also insist upon the use of more restricted rules to improve yield.

SPICE (Simulation Program with Integrated Circuit Emphasis)[1][2] is a general-purpose, open source analog electronic circuit simulator. It is a powerful program that is used in integrated circuit and board-level design to check the integrity of circuit designs and to predict circuit behavior.

GDSII stream format, common acronym GDSII, is a database file format which is the de facto industry standard for data exchange of integrated circuit or IC layout artwork. It is a binary file format representing planar geometric shapes, text labels, and other information about the layout in hierarchical form. The data can be used to reconstruct all or part of the artwork to be used in sharing layouts, transferring artwork between different tools, or creating photomasks.

*** It would be interesting to know if POET and Synopsis have plans for Interoperable Process Design Kits (iPDKs) http://www.synopsys.com/Company/Publications/SynopsysInsight/Pages/Art1-ipdks-IssQ3-11.aspx?cmp=Insight-I3-2011-Art1

Summary
Digital designers often characterize analog design as "black magic" because of its difficulty and complexity. Analog and custom design teams still do much of their design with less automation than their colleagues working in the digital domain. However, interoperable PDKs and interoperable design constraints give analog and custom design teams a significant productivity boost as they enable design teams to more easily reuse blocks and gain access to the latest tools, flows and technology processes.

Leading foundries around the world see the value in investing in iPDKs, which is why TSMC, TowerJazz, Dongbu HiTek and LFoundry have joined IPL, and GlobalFoundries has chosen to work with Synopsys to deliver iPDKs for its latest processes.