Interesting post by FJ (on the other board) - thanks FJ
The article at the bottom is pretty good at explaining the technical challenges that confront the fabrication of 3d designs namely the finFET. But what becomes ultimately more important is the limitations and issues of the design even if yields and fabrication process problems are overcome. FinFET’s are much less efficient to transfer of heat. So one of the most fundamental issues confronting higher density through the finFET becomes a greater issue leading to a much steeper aging curve (reduced life) and requiring increased control to avoid localized thermal stress (hot spots). Leakage is reduced so that is big improvement but I think it starts to look like a zero sum gain. “finFETs generate more localized heat. Given that a 16nm finFET has 25% more drive capability compared with a 20nm planar transistor, plus a higher gate density, this results in 25% to 30% more power density in a local area” http://semiengineering.com/heat-problems-grow-with-finfets-and-3d-ics/ The article above is excellent at capturing the real problems confronting the finFET design. The article below discusses the process issues.
http://www.eetimes.com/author.asp?section_id=36&doc_id=1321674&page_number=1
