Other advantages of III-V over silicon is its lower operating voltage -- as low as 0.3 volts with electron mobilities as high as 12,000 cm2/ (V·s) achieved by strained quantum wells -- lowering the power required to operate III-V chips by 10 times or more, according to POET.
Winning!!
Things are about to heat up.
If you have all the D&D and you are lining this all up, I bet you are thinking exactly what i am.
Remember the days of taylor's law? The company has gone in a completely different direction. Adding to moore's law instead.
There are reasons for the reversal of metrics and the addition of ajit at the same time. Seems like smart business to me. (I wont go into my opinion too much, just harp on the facts)
So 10x minimum power savings
problems that have prevented them from already taking over silicon -- namely, the lack of enhancement devices for digital circuits and of the p-channel transistor for complementary design. However, POET has found a way to grow successive layers of InGaAs on GaAs wafers, each with a little more indium, until they achieve a substrate on which both n-type and p-type transistors can be fabricated.
So Now that thats done.
POET has high hopes that it can eventually boost the n-types to greater than 12,000 in order to realize extremely high digital logic rates with complementary HFETs.
Man im glad we have Ajit
The channels of POET's transistors are InGaAs, which theoretically could reach 40,000 cm2/ (V·s) if the gallium was reduced to zero (pure bulk InAs). That however is not achievable, according to POET, although it is getting as close as it can. Thus far channels of 53% indium have been achieved and the company believes that 80% indium is ultimately possible.
hmmm
"We achieved these results by changing the lattice constant in a unique metamorphic way that fools nature," Taylor tells EE Times. "First we start with GaAs substrate, then we layer on top of that one micron strained layers of InGaAs over and over until we reach a layer that has natural quantum wells corresponding to the lattice constant of InP. It's all a question of the compositional control enabled by MBE [Molecular-beam epitaxy]."
Great! and we have patents so Booyah.
POET has a deal with a third-party foundry to demonstrate a 100 nanometer process later this year and a 40 nanometer process by 2015. Those figures sound like they are behind silicon, which is already down to 20 nanometers and, at Intel, down to 14 nanometers. But POET argues that the comparison is not fair. Instead its 40 nanometer process should be compared to 14 and 10 nanometer in silicon.
And that is just the beginning. Great article and finally some disclosure.
Confident bunch our management team has been and remains to be. My moneys on Ptk.
Some work to do for sure, Speaking of work let me get back to it. Ive been distracted all day! Thanks for hearing me out, Good luck Longs.
