Not much inside:
SUMMARY OF MATERIAL CHANGE
The Company announced a collaboration with Synopsys, Inc. to develop an advanced model and first Process Design Kit (PDK) of POET’s electrical devices (PET) targeting the 40-nm technology node widely used for highly integrated systems-on-chip (SoC). Through this collaboration, the Company will use Synopsys’ TCAD toolset and services to continue to develop the PET and POET PDKs. The PET PDK milestone (MS-12) focuses on devices requiring only the electronic subset of the POET devices and processes. Synopsys will provide expertise and services to the POET team, enabling the Company to expedite the design process (see Schedule “A”).
The Company also announced an agreement with a “3rd party foundry” to reproduce and enhance repeatability of the 100-nm scale results obtained at the Company’s lab. The “3rd party foundry” will also assist shrinking the 100-nm PET devices and process to a 40-nm feature size (see Schedule “B”).
Management of the Company now believes that: (a) it has the right collaboration in place with Synopsys and its “3rd party foundry” to model its technology down to 40-nm and correlate its process to real physical device measurements; (b) this should provide the results needed to showcase POET technology to potential customers at the optimum node for the POET platform, (c) synergistic benefits may be expected from having parallel operations with the same end target.
http://www.sec.gov/Archives/edgar/data/1437424/0001104659-14-064479-index.htm
