I wish Joel would explain what he thinks is intrinsically better about bringing GaAs chips down to 40nm. I would have thought he would be harping on the fact that GaAs wafers are only 6" when Si is supposed to go to 450mm...
Of course a 40nm POET GaAs chip would be better than a 90nm POET GaAs chip - you can put more on a chip of the same size and each transistor should require less power. But when Taylor goes on record saying that GaAs will outperform Si CMOS when it scales below 200nm, you choose to either believe him or not.
What you don't do is insist that it has to be scaled to 40nm simply because smaller numbers are better. I thought we made it clear that POET and CMOS are apples and oranges. And it's especially ironic that he comments this way in the section just below the article he wrote about the difficulties of scaling below 14nm. Is smaller really better?
I don't know, I kind of like the idea that POET will have some room to shrink over the years without worrying about developing special processes to push it below current limits. Isn't that part of the appeal?
Also, I don't know why he doesn't call Chris and arrange to chat with Lee or Geoff.
